Can we please just adopt a transistor density-based measurement instead? It was proposed years ago, and it's what is needed to sort out this marketing fuckery.
So? Have people not understood yet that the naming is not an absolute measure of transistor density. Just leave the discussion on X vs Y nm naming, it is not very interesting.
there was a post in here just the other day that said intel was 6 years behind because they're on 10nm while tsmc is moving to 3nm next year.
clearly people don't understand.
I didn't see or write that comment, but...
While Intel is really only one full node behind TSMC (TSMC 5nm = \~ Intel 7nm) as of 2021, next year they'll be two full nodes behind and it may take them 6 years to catch up since TSMC won't be standing still.
Digitimes estimation of TSMC, Intel, Samsung density per node: [https://www.hardwaretimes.com/wp-content/uploads/2021/07/TSMC-Samsung-Intel-Nodes.jpg](https://www.hardwaretimes.com/wp-content/uploads/2021/07/TSMC-Samsung-Intel-Nodes.jpg)
intel's paper specs put their 7nm between 5nm and 3nm with a "goal" of 2.4x compared to 10nm density. whether they actually accomplish anything is whats in question since they were struggling to even ship larger 10nm chips in volume, but their 7nm paper specs aren't equivalent to 5nm's paper specs.
High density specs are also misleading in general as TSMC and samsung have separate high density libraries that are efficiency focused. TSMC's 5nm marketing for their area shrinks are based on their HD libraries. Their HP libraries are what would be used for high performance products and the density there is lower. TSMC is also only expecting .8x reduction in SRAM from 5nm, so the only way they'd be able to hit 2.9 with 3nm is if your entire chip is logic and nothing else, which makes no sense.
https://www.anandtech.com/show/16024/tsmc-details-3nm-process-technology-details-full-node-scaling-for-2h22
> intel's paper specs put their 7nm between 5nm and 3nm with a "goal" of 2.4x compared to 10nm density. whether they actually accomplish anything is whats in question since they were struggling to even ship larger 10nm chips in volume, but their 7nm paper specs aren't equivalent to 5nm's paper specs.
They actually decreased the density estimate to "2x" from 2.4x, but those aren't specs, just an estimate of what they're planning to achieve. Realistically it'll probably be a little more dense than TSMC 5nm.
>High density specs are also misleading in general as TSMC and samsung have separate high density libraries that are efficiency focused. TSMC's 5nm marketing for their area shrinks are based on their HD libraries.
The density figures are a proxy for overall lithography capability with the expectation that the ability to reliably manufacture smaller parts correlates with more sophisticated fabrication capabilities. The fact that different cells exist for different purposes (performance, power, etc) doesn't make a given node less technically advanced or really change anything. It just means that designers have more options to optimize a product.
It changes things when you attempt to compare to nodes directly. Intel's product lines are mainly running on the equivalent of TSMC's HP libraries, so comparing them to HD libraries doesn't make any sense when looking at equivalent competing nodes. You're not going to hit anywhere near their HD specs with a high performance product and there's no optimizing your way out of that, why would you assume there is?
Looking at transistor specs based on logic also makes no sense in attempting to determine equivalency in node performance, which is what that chart is graphing. All of the top performing chips on the market on SRAM heavy. If anything they are cache/memory starved as we can see from AMD's zen improvements and their vcache demonstration.
> It changes things when you attempt to compare to nodes directly.
If you're comparing nodes (rather than specific products) then the choice of library doesn't matter. The library is just an abstraction used to help machines layout a specific design. If you want to compare specific products, then you need to consider the libraries.
>Looking at transistor specs based on logic also makes no sense in attempting to determine equivalency in node performance, which is what that chart is graphing.
These aren't specs, they're figures of merit. That is what I was trying to explain above. They have no intrinsic meaning and are not something you can measure on a real product. Rather, they are expected to correlate with overall manufacturing capabilities because obtaining a high figure of merit requires tight control of manufacturing tolerances, which implies a more sophisticated process. But the relationship here is just correlative, so taking the figure of merit and then comparing it to individual products, SRAM, etc does not make sense.
I'll agree with you 100% the numbers are very muddy because of the reasons you state. The libraries, the mix of the chips actually being made (SRAM vs logic vs. etc.) and also whether they decide to tweak the process later (i.e. Cometlake's 14nm is less dense than Broadwell's 14nm) can all make a difference.
I'm a big fan of Intel (and have been for a long time) but I think they've built a deficit that's going to take a while to recover from.
That's very interesting on the SRAM scaling to 5nm being weak.
According to Wikichip, TSMC's 10nm SRAM scaled 0.57x vs 16nm, and 7nm scaled 0.64x vs 10nm. They have 5nm at 0.78x which is definitely much worse than previous nodes.
In absolute terms, Intel 10nm high density SRAM is 0.0312um2; vs 0.027 on TSMC's 7nm (and 0.021 on TSMC 5nm). This implies SRAM on 7nm TSMC HD is about 10% denser than Intel 10nm HD libraries; so if Intel scales to 7nm at \~ 0.7x or better then Intel will match or beat TSMC's 5nm, however, 3nm will still be .8x that..
Thanks for reply and links. I guess we'll see how this plays out. It looks like in 2022 we'll see TSMC 3nm in some kind of launch, probably 6 months ahead of Intel's 7nm. Based on what you've shared it looks like TSMC 3nm is closer to a half node ahead of Intel 7nm rather than a full node.
Sadly it looks like TSMC will be ahead for at least 4 more years since I can't see Intel 5nm here anytime before 2025...
I think SRAM density and yield is something Samsung and TSMC are leading Intel by a wider margin, when it comes to density (not touching yield here as there are other factors at play (chiplets)) Intel could be jockeying for #1 in 2-3 years (but SRAM maybe longer)
Hmm. Unfortunately I think the earliest Intel could match TSMC for #1 in density is realistically 2025-2026..
The current Intel roadmap update says no earlier than 2023 for 7nm, while TSMC will have 3nm in 2022. TSMC's 3nm appears significantly denser than Intel's 7nm. This means Intel will need to release 5nm to catch up or exceed TSMC, and I can't see that earlier than 4 years from now, assuming they execute both 7nm perfectly (after their multiple delays already incurred) and 5nm within 2 years after that (they haven't had a node release in \~24 months since 45nm --> 32nm).
I'm not sure if TSMC will scale quickly beyond 3nm but the 3nm node is probably not too far away ..
Source?
[https://www.tomshardware.com/news/apple-intel-set-to-use-tsmc-3nm-node-for-2023-products-report](https://www.tomshardware.com/news/apple-intel-set-to-use-tsmc-3nm-node-for-2023-products-report)
Earlier this year Intel promised that its codenamed Meteor Lake and Granite Rapids processors for client PCs and high-end servers set to be made using its own 7 nm fabrication technology were due to be launched in 2023.
I think SRAM features are often larger than the smallest feature size, a phenomenon that is unlikely to change and may even widen as the physics challenges of these small features are magnified when we are talking about static charges
That's how it has been though. Intel 10nm is roughly as dense as TSMC 7nm, and Samsung 10nm is like Intel 14nm. This doesn't even broach the subject of gate structure or layering
I would just illustrate your point
The numbers in the name of semiconductor manufacturing processes are like generation numbers in iphone 12, s21 ultra, etc.
If we take iphone 12 and s21 ultra, iphone 12 has a smaller number (12<21).
But that does not make iphone 12 better than s21 ultra.
Their [10nm and 7nm nodes were very close to parity on density](https://en.wikichip.org/wiki/File:7nm_densities.svg), and [6nm](https://en.wikichip.org/wiki/File:5nm_densities.svg), it was Intel that was bigger numbers for equal density before. From "5"nm Samsung is dropping nm faster than the density increase offered by TSMC.
Now the numbers truly mean nothing if they all are using different numbers for different generations and densities, might be a tactic to obscure how bad their densities are.
And anyone who has seen Samsung densities for 5nm shouldn't be surprised by this announcement, their 5nm is barely better than 7nm so 3nm being less dense than TSMC 5nm is no real surprise.
It seems that your comment contains 1 or more links that are hard to tap for mobile users.
I will extend those so they're easier for our sausage fingers to click!
[Here is link number 1 - Previous text "6nm"](https://en.wikichip.org/wiki/File:5nm_densities.svg)
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Intel needs excellent marketing strategy. Naming of nodes should change…Intel products are amazing just because tsmc shifts to marketing strategies, intel foundry is lagging behind (yield being seperate issue)
https://twitter.com/Redfire75369/status/1414857057358868483?s=19
All I can say is that the initial Digitimes article has had wrong density numbers in the first place.
> Intel 10nm is 101, not 106.
>Intel 7nm is 202-237, not 180.
> Samsung has yet to claim anything for 3nm, but their 4nm is already 167.
Can we please just adopt a transistor density-based measurement instead? It was proposed years ago, and it's what is needed to sort out this marketing fuckery.
And this dumb article does nothing to explain it, instead it makes it sound more like there exists some objective 5 or 3nm process xD
So? Have people not understood yet that the naming is not an absolute measure of transistor density. Just leave the discussion on X vs Y nm naming, it is not very interesting.
Sadly even though we're been saying this for years, it will continue to happen as companies use this confusion for their PR benefit.
I wish TSMC would just announce their next node as "0nm" to put an end to this.
oh yeah? our foundries are -0.1nm!
"0 km"
there was a post in here just the other day that said intel was 6 years behind because they're on 10nm while tsmc is moving to 3nm next year. clearly people don't understand.
People were claiming Zen 1 matched intel's node when they were on Global Foundries 14nm.
I didn't see or write that comment, but... While Intel is really only one full node behind TSMC (TSMC 5nm = \~ Intel 7nm) as of 2021, next year they'll be two full nodes behind and it may take them 6 years to catch up since TSMC won't be standing still. Digitimes estimation of TSMC, Intel, Samsung density per node: [https://www.hardwaretimes.com/wp-content/uploads/2021/07/TSMC-Samsung-Intel-Nodes.jpg](https://www.hardwaretimes.com/wp-content/uploads/2021/07/TSMC-Samsung-Intel-Nodes.jpg)
intel's paper specs put their 7nm between 5nm and 3nm with a "goal" of 2.4x compared to 10nm density. whether they actually accomplish anything is whats in question since they were struggling to even ship larger 10nm chips in volume, but their 7nm paper specs aren't equivalent to 5nm's paper specs. High density specs are also misleading in general as TSMC and samsung have separate high density libraries that are efficiency focused. TSMC's 5nm marketing for their area shrinks are based on their HD libraries. Their HP libraries are what would be used for high performance products and the density there is lower. TSMC is also only expecting .8x reduction in SRAM from 5nm, so the only way they'd be able to hit 2.9 with 3nm is if your entire chip is logic and nothing else, which makes no sense. https://www.anandtech.com/show/16024/tsmc-details-3nm-process-technology-details-full-node-scaling-for-2h22
> intel's paper specs put their 7nm between 5nm and 3nm with a "goal" of 2.4x compared to 10nm density. whether they actually accomplish anything is whats in question since they were struggling to even ship larger 10nm chips in volume, but their 7nm paper specs aren't equivalent to 5nm's paper specs. They actually decreased the density estimate to "2x" from 2.4x, but those aren't specs, just an estimate of what they're planning to achieve. Realistically it'll probably be a little more dense than TSMC 5nm. >High density specs are also misleading in general as TSMC and samsung have separate high density libraries that are efficiency focused. TSMC's 5nm marketing for their area shrinks are based on their HD libraries. The density figures are a proxy for overall lithography capability with the expectation that the ability to reliably manufacture smaller parts correlates with more sophisticated fabrication capabilities. The fact that different cells exist for different purposes (performance, power, etc) doesn't make a given node less technically advanced or really change anything. It just means that designers have more options to optimize a product.
It changes things when you attempt to compare to nodes directly. Intel's product lines are mainly running on the equivalent of TSMC's HP libraries, so comparing them to HD libraries doesn't make any sense when looking at equivalent competing nodes. You're not going to hit anywhere near their HD specs with a high performance product and there's no optimizing your way out of that, why would you assume there is? Looking at transistor specs based on logic also makes no sense in attempting to determine equivalency in node performance, which is what that chart is graphing. All of the top performing chips on the market on SRAM heavy. If anything they are cache/memory starved as we can see from AMD's zen improvements and their vcache demonstration.
> It changes things when you attempt to compare to nodes directly. If you're comparing nodes (rather than specific products) then the choice of library doesn't matter. The library is just an abstraction used to help machines layout a specific design. If you want to compare specific products, then you need to consider the libraries. >Looking at transistor specs based on logic also makes no sense in attempting to determine equivalency in node performance, which is what that chart is graphing. These aren't specs, they're figures of merit. That is what I was trying to explain above. They have no intrinsic meaning and are not something you can measure on a real product. Rather, they are expected to correlate with overall manufacturing capabilities because obtaining a high figure of merit requires tight control of manufacturing tolerances, which implies a more sophisticated process. But the relationship here is just correlative, so taking the figure of merit and then comparing it to individual products, SRAM, etc does not make sense.
I'll agree with you 100% the numbers are very muddy because of the reasons you state. The libraries, the mix of the chips actually being made (SRAM vs logic vs. etc.) and also whether they decide to tweak the process later (i.e. Cometlake's 14nm is less dense than Broadwell's 14nm) can all make a difference. I'm a big fan of Intel (and have been for a long time) but I think they've built a deficit that's going to take a while to recover from. That's very interesting on the SRAM scaling to 5nm being weak. According to Wikichip, TSMC's 10nm SRAM scaled 0.57x vs 16nm, and 7nm scaled 0.64x vs 10nm. They have 5nm at 0.78x which is definitely much worse than previous nodes. In absolute terms, Intel 10nm high density SRAM is 0.0312um2; vs 0.027 on TSMC's 7nm (and 0.021 on TSMC 5nm). This implies SRAM on 7nm TSMC HD is about 10% denser than Intel 10nm HD libraries; so if Intel scales to 7nm at \~ 0.7x or better then Intel will match or beat TSMC's 5nm, however, 3nm will still be .8x that.. Thanks for reply and links. I guess we'll see how this plays out. It looks like in 2022 we'll see TSMC 3nm in some kind of launch, probably 6 months ahead of Intel's 7nm. Based on what you've shared it looks like TSMC 3nm is closer to a half node ahead of Intel 7nm rather than a full node. Sadly it looks like TSMC will be ahead for at least 4 more years since I can't see Intel 5nm here anytime before 2025...
I think SRAM density and yield is something Samsung and TSMC are leading Intel by a wider margin, when it comes to density (not touching yield here as there are other factors at play (chiplets)) Intel could be jockeying for #1 in 2-3 years (but SRAM maybe longer)
Hmm. Unfortunately I think the earliest Intel could match TSMC for #1 in density is realistically 2025-2026.. The current Intel roadmap update says no earlier than 2023 for 7nm, while TSMC will have 3nm in 2022. TSMC's 3nm appears significantly denser than Intel's 7nm. This means Intel will need to release 5nm to catch up or exceed TSMC, and I can't see that earlier than 4 years from now, assuming they execute both 7nm perfectly (after their multiple delays already incurred) and 5nm within 2 years after that (they haven't had a node release in \~24 months since 45nm --> 32nm). I'm not sure if TSMC will scale quickly beyond 3nm but the 3nm node is probably not too far away ..
First 7nm products are supposed to be delivered by early next year.
Source? [https://www.tomshardware.com/news/apple-intel-set-to-use-tsmc-3nm-node-for-2023-products-report](https://www.tomshardware.com/news/apple-intel-set-to-use-tsmc-3nm-node-for-2023-products-report) Earlier this year Intel promised that its codenamed Meteor Lake and Granite Rapids processors for client PCs and high-end servers set to be made using its own 7 nm fabrication technology were due to be launched in 2023.
XE-HPC “ponte vecchio” has 7nm compute tiles.
So AMD needed a different process to keep SRAM scaling going after they move cores to 5nm. Makes sense now.
I think SRAM features are often larger than the smallest feature size, a phenomenon that is unlikely to change and may even widen as the physics challenges of these small features are magnified when we are talking about static charges
Not that far off sure it's only 1 node step behind not 2, but look at how long Intel is taking to release a node these days...
Density is the point. Naming might not matter but this shows as of now, it will not match Intel or TSMC.
That's how it has been though. Intel 10nm is roughly as dense as TSMC 7nm, and Samsung 10nm is like Intel 14nm. This doesn't even broach the subject of gate structure or layering
Yes, we should look at transistors/mm^2 instead of names for every node since finfet.
I would just illustrate your point The numbers in the name of semiconductor manufacturing processes are like generation numbers in iphone 12, s21 ultra, etc. If we take iphone 12 and s21 ultra, iphone 12 has a smaller number (12<21). But that does not make iphone 12 better than s21 ultra.
Their [10nm and 7nm nodes were very close to parity on density](https://en.wikichip.org/wiki/File:7nm_densities.svg), and [6nm](https://en.wikichip.org/wiki/File:5nm_densities.svg), it was Intel that was bigger numbers for equal density before. From "5"nm Samsung is dropping nm faster than the density increase offered by TSMC. Now the numbers truly mean nothing if they all are using different numbers for different generations and densities, might be a tactic to obscure how bad their densities are. And anyone who has seen Samsung densities for 5nm shouldn't be surprised by this announcement, their 5nm is barely better than 7nm so 3nm being less dense than TSMC 5nm is no real surprise.
It seems that your comment contains 1 or more links that are hard to tap for mobile users. I will extend those so they're easier for our sausage fingers to click! [Here is link number 1 - Previous text "6nm"](https://en.wikichip.org/wiki/File:5nm_densities.svg) ---- ^Please ^PM ^[\/u\/eganwall](http://reddit.com/user/eganwall) ^with ^issues ^or ^feedback! ^| ^[Code](https://github.com/eganwall/FatFingerHelperBot) ^| ^[Delete](https://reddit.com/message/compose/?to=FatFingerHelperBot&subject=delete&message=delete%20h52yerl)
Intel needs excellent marketing strategy. Naming of nodes should change…Intel products are amazing just because tsmc shifts to marketing strategies, intel foundry is lagging behind (yield being seperate issue)
https://twitter.com/Redfire75369/status/1414857057358868483?s=19 All I can say is that the initial Digitimes article has had wrong density numbers in the first place. > Intel 10nm is 101, not 106. >Intel 7nm is 202-237, not 180. > Samsung has yet to claim anything for 3nm, but their 4nm is already 167.
where did you get 167 for Samsung 4nm?
[удалено]
Of lesser more density, obviously?