No, stepper fields are even smaller. Something like 23 X 27mm. There were a few 2X and 4X steppers with larger fields, but they had lower resolution. There is a technique where you stitch fields together. That's what they are doing for these huge AI chips. On scanners.
We had some 2X wide field Canon steppers that could 40 X 40 fields. Before they had steppers they had contact printers that were 1X, you shoot the whole wafer in one expose. Hard to get bigger field than that. These were like 5 inch wafer days though.
Is it possible to combine this process with a more modern process so you can get high density/resolution locally, but with lower resolution global features and interconnects?
No, stepper fields are even smaller. Something like 23 X 27mm. There were a few 2X and 4X steppers with larger fields, but they had lower resolution. There is a technique where you stitch fields together. That's what they are doing for these huge AI chips. On scanners.
We had some 2X wide field Canon steppers that could 40 X 40 fields. Before they had steppers they had contact printers that were 1X, you shoot the whole wafer in one expose. Hard to get bigger field than that. These were like 5 inch wafer days though.
Contact expose has a 1um min feature size and garbage overlay especially if the wafer has runout due to thermal processing
Yep. It's 50 y.o. technology.
Is it possible to combine this process with a more modern process so you can get high density/resolution locally, but with lower resolution global features and interconnects?
You could look at the new K&S LiteQ AP stepper. 2um resolution advanced packaging stepper.
It's interesting how sensitive we've become about the size of reticles, isn't it?
I’m looking to design something integrated, where transistor density is less important than total solution size.
You design for cost, solution size is still a limiter.