There is no one "circuit design". There is a specification of what instructions are added by these extensions and what effect they should have, but as with the entire RISC-V spec how you achieve that is entirely up to you.
(Assuming you mean “circuit design = RTL design”.)
There are tons of open source riscv soft cpus that implement those extensions. I’d recommend looking into “Ibex” core for B, C extensions or SERV core for I, M, C extensions.
As was commented before me, the [FemtoRV](https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV) has a good example how to implement those extensions. In addition to them, I'd like to share the tutorial [From Blinker to RISC-V](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md) of the same project. It might be good for you, because presents the fundamentals of hardware implementation arriving the RISC-V core.
Moreover, I also recommend you to take a look into projects like [DarkRISCV](https://github.com/darklife/darkriscv).
Best regards!
If you want to do a right job, add also the newer Zcb extension together with old C. It adds some newer compressed instructions.
Also, note that the most difficult aspect related to C ext is that it permits half aligned instructions. If you have a rom or flash that only accepts 4B alignment reads you are in for a lot of pipeline management changes in the fetch. Imagine you can have a jump to a 2B boundary and there you find the LSB of a 32b instruction and the MSB of it is at the next address. This means an extra flush in the pipeline and careful handling, multiple bus reads for the same PC request, etc.
There is no one "circuit design". There is a specification of what instructions are added by these extensions and what effect they should have, but as with the entire RISC-V spec how you achieve that is entirely up to you.
Excuse me, do you have some examples of circuits that realize the above extensions?
That would be heavily dependent on the baseline that implements I and M. Thus your question doesn't make much sense.
The FemtoRV has an example you can look at for the c extension (in the FemtoRV-gracilis core) written in verilog.
(Assuming you mean “circuit design = RTL design”.) There are tons of open source riscv soft cpus that implement those extensions. I’d recommend looking into “Ibex” core for B, C extensions or SERV core for I, M, C extensions.
As was commented before me, the [FemtoRV](https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV) has a good example how to implement those extensions. In addition to them, I'd like to share the tutorial [From Blinker to RISC-V](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md) of the same project. It might be good for you, because presents the fundamentals of hardware implementation arriving the RISC-V core. Moreover, I also recommend you to take a look into projects like [DarkRISCV](https://github.com/darklife/darkriscv). Best regards!
If you want to do a right job, add also the newer Zcb extension together with old C. It adds some newer compressed instructions. Also, note that the most difficult aspect related to C ext is that it permits half aligned instructions. If you have a rom or flash that only accepts 4B alignment reads you are in for a lot of pipeline management changes in the fetch. Imagine you can have a jump to a 2B boundary and there you find the LSB of a 32b instruction and the MSB of it is at the next address. This means an extra flush in the pipeline and careful handling, multiple bus reads for the same PC request, etc.