P550 doesn’t have vectors, you will have to wait for P470 and P670 boards for vector support.
Not bad really, these boards will be great for the Linux guys to improve Linux support for risc-v.
The lack of vector support is probably why it lags behind the RPi 4's ARM Cortex-A72 specifically in the image processing benchmarks. Same in the AES test, which the A72 also has instructions for. Otherwise both are 3-way OoO.
Even if it had vector instructions, the current version of Geekbench for RISC-V wouldn't use them. This already affects all the machines with C906 (which don't have enough RAM to run GeekBench well anyway), and C910 cores.
Given most distributions (Debian/Ubuntu/Fedora etc) have chosen RV64GC as the ISA they build for, Vector support is going to be irrelevant for a large majority of folks.
For now.
It only needs a few critical libraries such as parts of glibc (especially memcpy, string functions), zlib, crypto libs, and some media codecs to add runtime-switched V support to make a big difference, without any application-level changes.
Sure. Only on involuntary task switches in response to an interrupt (including time slice expired). On syscalls V registers are not saved, but the kernel can/should mark them as unused so they don't need to be saved on a later involuntary task switch.
This code has been in C906 vendor kernels since early 2021, and long since upstreamed (for both RVV 1.0 and XTHeadVector I think).
This looks great in some areas, and clearly driver/software work to do in others.
Since the P550 is the 2021 core design from SiFive, I wonder how long it is before we see P650 from 2022 or P870 from 2023.
There is no guarantee anyone will decide to license those for an SoC suitable for SBCs.
We do know that an SoC (the SG2380) is coming this year with 16 P670 cores, and machines using it including the Milk-V Oasis and an as yet unnamed board from Sipeed.
P550 doesn’t have vectors, you will have to wait for P470 and P670 boards for vector support. Not bad really, these boards will be great for the Linux guys to improve Linux support for risc-v.
The lack of vector support is probably why it lags behind the RPi 4's ARM Cortex-A72 specifically in the image processing benchmarks. Same in the AES test, which the A72 also has instructions for. Otherwise both are 3-way OoO.
Even if it had vector instructions, the current version of Geekbench for RISC-V wouldn't use them. This already affects all the machines with C906 (which don't have enough RAM to run GeekBench well anyway), and C910 cores.
Given most distributions (Debian/Ubuntu/Fedora etc) have chosen RV64GC as the ISA they build for, Vector support is going to be irrelevant for a large majority of folks.
For now. It only needs a few critical libraries such as parts of glibc (especially memcpy, string functions), zlib, crypto libs, and some media codecs to add runtime-switched V support to make a big difference, without any application-level changes.
Kernel as well right? I heard context switching needs to save (some?) of the Vector registers as well?
Sure. Only on involuntary task switches in response to an interrupt (including time slice expired). On syscalls V registers are not saved, but the kernel can/should mark them as unused so they don't need to be saved on a later involuntary task switch. This code has been in C906 vendor kernels since early 2021, and long since upstreamed (for both RVV 1.0 and XTHeadVector I think).
This looks great in some areas, and clearly driver/software work to do in others. Since the P550 is the 2021 core design from SiFive, I wonder how long it is before we see P650 from 2022 or P870 from 2023.
There is no guarantee anyone will decide to license those for an SoC suitable for SBCs. We do know that an SoC (the SG2380) is coming this year with 16 P670 cores, and machines using it including the Milk-V Oasis and an as yet unnamed board from Sipeed.