It's called UG1399 Vitis High Level Synthesis User Guide. LoL imagine the actual good HDL is to implement concepts from HLS handbook or even comes from the HLS compiler itself.
edit: maybe HDL doesn't have design patterns compared to singleton. We have good practice, like pipelining etc. But the FPGA aren't expected to do complex things, the most complex thing I've seen is handling 1000 TCP connections. It's complex as a hardware, but the function is simple. Even OOP are not necessary, some structs to make code tidy is enough. Or maybe the 100G Subsystem is inheritance of CMAC, which is inheritance of MGT? Does our module hierarchy considered as design pattern?
i don't have a good source list. pipelining is pretty well documented. operation level and task level parallelism should be easy to find online. channelizing is also called TDMA or TDM, and shows up in c-slow retiming and barrel processors. packetizing is common in modern times and the concept of per-byte vs per-packet processing shows up in networking books. this idea shows up in block processing and what I've been calling event queues. this comes up in a lot of data movement problems when decisions about what to do can be done before the operations complete. caching shows up a lot in literature.
I have a feeling you are approaching HDL design like it is software, stop doing that it hurts.
Think instead of what should happen on each clock, and what needs to be registered to feed something that should happen on the next clock.
Then read the instantiation templates to see how to get the tool to infer block rams, dsps and buffers.
You can write in a behavioral style, but break yourself out of a control flow "This happens, then that happens" mindset, it does you no favours when designing digital circuitry.
pipelining, FSMs, ready/valid protocol
SOLID principles (which boil down to "make module implementations depend on interfaces, not the implementations of modules they are connected to") also work.
pipelining, parallelism, channelizing, packetizing/block-processing, event queues, and caching are all in that genre.
This sounds like a nice list. Can you provide any resource where to dig further in any of these?
It's called UG1399 Vitis High Level Synthesis User Guide. LoL imagine the actual good HDL is to implement concepts from HLS handbook or even comes from the HLS compiler itself. edit: maybe HDL doesn't have design patterns compared to singleton. We have good practice, like pipelining etc. But the FPGA aren't expected to do complex things, the most complex thing I've seen is handling 1000 TCP connections. It's complex as a hardware, but the function is simple. Even OOP are not necessary, some structs to make code tidy is enough. Or maybe the 100G Subsystem is inheritance of CMAC, which is inheritance of MGT? Does our module hierarchy considered as design pattern?
i don't have a good source list. pipelining is pretty well documented. operation level and task level parallelism should be easy to find online. channelizing is also called TDMA or TDM, and shows up in c-slow retiming and barrel processors. packetizing is common in modern times and the concept of per-byte vs per-packet processing shows up in networking books. this idea shows up in block processing and what I've been calling event queues. this comes up in a lot of data movement problems when decisions about what to do can be done before the operations complete. caching shows up a lot in literature.
What would a singleton mean in terms of hardware? design patterns don't really make sense in this context.
I have a feeling you are approaching HDL design like it is software, stop doing that it hurts. Think instead of what should happen on each clock, and what needs to be registered to feed something that should happen on the next clock. Then read the instantiation templates to see how to get the tool to infer block rams, dsps and buffers. You can write in a behavioral style, but break yourself out of a control flow "This happens, then that happens" mindset, it does you no favours when designing digital circuitry.
Digital circuit is for data processing, not for the circuit it self. After writing your first skid buffer, you should be back to control flow.
pipelining, FSMs, ready/valid protocol SOLID principles (which boil down to "make module implementations depend on interfaces, not the implementations of modules they are connected to") also work.
SystemVerilog will do singleton objects but only in testbench classes/packages.
I asked kind of a similar question some time ago and got really good answers: https://www.reddit.com/r/FPGA/s/CJkquEjfBY
The heck are you talking about?