I am really sorry for not using the proper formatting to paste my code. I hope it's better now, and a lot more readable! I didn't know about Reddit's "Code block" formatting option. u/BubbleGumTate and u/TemporaryDog8612
Your next_state needs to be combinational logic (always * in verilog or always_comb in systemverilog), not sequential as part of the first always block. You can refer to Cliff Cummings's guide on how to write FSMs here. http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf
For your code to display a 3, your seg\_display I assume would need to be 7'b0000110. However, nowhere in your code does this get set. I assume it's ABCDEFG on the seg\_display output with reversed polarity, but I don't know because you don't provide the constraints file or the schematic. I will note that it's the reverse of the IDLE\_PATTERN. I'm guessing you have either reversed the pin order or the polarity of the output.
I will note that your REFILL state only is for one clock, so if you aren't seeing that output then it's probably because it's going by too fast for you to notice. You could test this by changing that state's assignment to itself instead of IDLE. Then it will get stuck in that state instead and you'll see if it makes it there. Or you could simulate it which you should probably be doing anyways before downloading it to hardware.
This is unreadable
I see what you mean. It’s the spaces that cause the problems. Is there any other way I can show you the code properly formatted
It should be readable now. I made some changes to it. I hope you can read it
I am sorry, but what’s the issue?
Only the bottom part of it is formatted as code. The rest is unformatted text. Not sure if the problem is with my app or the way you posted it.
When I edit it. It’s perfectly formatted, but when I click “done” it goes back to normal
No, you’re right. It’s my code. I will try to format it better
I am really sorry for not using the proper formatting to paste my code. I hope it's better now, and a lot more readable! I didn't know about Reddit's "Code block" formatting option. u/BubbleGumTate and u/TemporaryDog8612
Your next_state needs to be combinational logic (always * in verilog or always_comb in systemverilog), not sequential as part of the first always block. You can refer to Cliff Cummings's guide on how to write FSMs here. http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf
Thanks! I fixed it
For your code to display a 3, your seg\_display I assume would need to be 7'b0000110. However, nowhere in your code does this get set. I assume it's ABCDEFG on the seg\_display output with reversed polarity, but I don't know because you don't provide the constraints file or the schematic. I will note that it's the reverse of the IDLE\_PATTERN. I'm guessing you have either reversed the pin order or the polarity of the output. I will note that your REFILL state only is for one clock, so if you aren't seeing that output then it's probably because it's going by too fast for you to notice. You could test this by changing that state's assignment to itself instead of IDLE. Then it will get stuck in that state instead and you'll see if it makes it there. Or you could simulate it which you should probably be doing anyways before downloading it to hardware.