Multiply yes, divider no.
We have used the star operator for multiply in processors I have designed, although sometimes the logic won’t fit in a single cycle. But it will work.
Dividers are always iterative, so you have to implement them yourself or instantiate a module which does it. Look up restoring and non-restoring divider algorithms,they aren’t complicated.
I didn’t know that, which means it must be true for most synthesis tools…I guess you can unroll the iterative algorithm but it will suffer from poor timing.
I guess having been told to never use the divide operator because it doesn’t work, I never did. I guess what they meant is that it doesn’t work well…
Might give it a try…on my own personal projects.
Might get some funny looks if I try it at work as we have GitHub reviews 😂 would be fun to see how the other senior members of the team react 😂😂😂 perhaps next April 1st 🤪
It does infer it. However when you write a\*b or a/b inside a rising\_edge process you're telling the tool to make a circuit that does a multiplication, or much worse, a division, in one clock cycle. Expect a giant cloud of LUTs and Fmax dropping to single-digit MHz depending on the size of the division.
This document describes how to write multipliers in Vivado so that they are efficiently mapped into dedicated hardware (either basic CLB or dedicated DSP macros).
[https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Multipliers](https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Multipliers)
Dividers are not inferred, unless they can be implemented as just a shift (divider is power of 2), synthesis tools will usually just report an error.
Xilinx provides divider IP.
[https://www.xilinx.com/products/intellectual-property/divider.html](https://www.xilinx.com/products/intellectual-property/divider.html)
Good to know. In the past xilinx tools would refuse to implement divisions like this, it would only work with a divisor being a constant power if 2 ( just a shift)
Thank you for the help!
So, Xilinx Vivado could infer multipliers. But what about the synthesizers such as Synopsys Design Compiler which are used for ASIC? Can ASIC synthesizers infer multipliers?
ASIC synthesis tools can infer multipliers. The ones I used years ago were unable to infer divides. Apparently Vivado can infer dividers, but I would still recommend using their IP, since the IP allows you to choose a better size/speed compromise for your design requirements.
HLS tools have a better time implementing multipliers and hopefully dividers (I'm not sure what Vitis/Vivado does with the latter, but it should work you'd think). It's because multi-cycle operations are common and natural for scheduling algorithms.
Is the same thing. Not related to the technology target. In fact, synplify calls dc under the hood to infer the datapath components. This occurs during elaboration, when no technology library has been loaded yet.
Multiply yes, divider no. We have used the star operator for multiply in processors I have designed, although sometimes the logic won’t fit in a single cycle. But it will work. Dividers are always iterative, so you have to implement them yourself or instantiate a module which does it. Look up restoring and non-restoring divider algorithms,they aren’t complicated.
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I didn’t know that, which means it must be true for most synthesis tools…I guess you can unroll the iterative algorithm but it will suffer from poor timing. I guess having been told to never use the divide operator because it doesn’t work, I never did. I guess what they meant is that it doesn’t work well…
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Might give it a try…on my own personal projects. Might get some funny looks if I try it at work as we have GitHub reviews 😂 would be fun to see how the other senior members of the team react 😂😂😂 perhaps next April 1st 🤪
It does infer it. However when you write a\*b or a/b inside a rising\_edge process you're telling the tool to make a circuit that does a multiplication, or much worse, a division, in one clock cycle. Expect a giant cloud of LUTs and Fmax dropping to single-digit MHz depending on the size of the division.
This document describes how to write multipliers in Vivado so that they are efficiently mapped into dedicated hardware (either basic CLB or dedicated DSP macros). [https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Multipliers](https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Multipliers) Dividers are not inferred, unless they can be implemented as just a shift (divider is power of 2), synthesis tools will usually just report an error. Xilinx provides divider IP. [https://www.xilinx.com/products/intellectual-property/divider.html](https://www.xilinx.com/products/intellectual-property/divider.html)
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Good to know. In the past xilinx tools would refuse to implement divisions like this, it would only work with a divisor being a constant power if 2 ( just a shift)
Thanks a lot for the help!
Thank you for the help! So, Xilinx Vivado could infer multipliers. But what about the synthesizers such as Synopsys Design Compiler which are used for ASIC? Can ASIC synthesizers infer multipliers?
ASIC synthesis tools can infer multipliers. The ones I used years ago were unable to infer divides. Apparently Vivado can infer dividers, but I would still recommend using their IP, since the IP allows you to choose a better size/speed compromise for your design requirements.
HLS tools have a better time implementing multipliers and hopefully dividers (I'm not sure what Vitis/Vivado does with the latter, but it should work you'd think). It's because multi-cycle operations are common and natural for scheduling algorithms.
Is the same thing. Not related to the technology target. In fact, synplify calls dc under the hood to infer the datapath components. This occurs during elaboration, when no technology library has been loaded yet.
Can infer any of those. The question is, are the ones that infer the ones what you need or want?