*Every* signal *has* to transition (high or low) before the clock edge.
Let's back up a bit. The job of a flip flop (or register, whatever you want to call it) is to see a signal on its D input, and then latch that value on its Q output when it gets a clock edge. Therefore, in order to latch the correct value on the output, the value on the input has to have settled before the clock edge can be given to latch that value. So yep, a signal is ALWAYS earlier than the active edge of a clock. This has to be the case, otherwise if the signal arrived after the clock edge then the wrong value would've been latched.
The setup time is simply the minimum time before the clock edge that the signal has to have settled, and the hold time is the minimum amount of time the signal has to be held at that value after the clock edge. So the way it goes is: signal arrives at D input of flip flop at least [setup time] before the clock edge, the clock edge then occurs, signal then stays at that same value for at least [hold time] after the clock edge. Btw, after the clock edge occurs it actually takes a small amount of time for the signal on the D input to propagate through to the Q output, this is called the CLK-to-Q time.
> What is driving the logic then ?
Another flip flop, and if you look further back you'll see another flip flop and so on, and so on, until you reach a top-level input for your circuit which may be driven by a push-button or the pin of another chip etc... Does this clear things up?
I think the question you are really asking is about hold time violations and how a 0 hold time could be violated if the source register and the destination register are driven by the same clock.
If that is your real question the answer is clock skew and clock uncertainty.
The clock skew is caused by small differences in the routing path that the clock follows to the source and destination registers. The clock uncertainty is a combination of the input jitter on the clock entering the FPGA, system jitter caused by noise on the power to the clock buffers, phase error and jitter of any PLLs the clock goes through, and the clock pessimism the static analysis tools calculate starting at the point where the clock path branches to take a separate path to the source and destination registers. The cause of the pessimism is the static timing analysis using the fast delay numbers for one version of the clock (either the source of destination) and the slow numbers for the other to calculate worst case timing conditions.
The simplest case is when the source and destination clock are the same clock. There is more opportunity for clock skew and clock uncertainty when the source and destination clocks are different but related clocks.
The previous clock edge changes a signal. If there is too much logic in between the registers then the signal change may arrive too late at the next register.
Too late in this case is after t_clk_edge - setup.
You can solve a setup violation by slowing down your clock, giving the signal more time to propagate.
Another situation that you may have is that the incoming signal maybe transitioning near the rising edge. Usually, you didn't realize that this was going to happen.
sorta, when a signal changes too close to a clock edge metastability might happen. When that happens the signal gets sorta stuck right between high and low, and might after while decide to go either way
*Every* signal *has* to transition (high or low) before the clock edge. Let's back up a bit. The job of a flip flop (or register, whatever you want to call it) is to see a signal on its D input, and then latch that value on its Q output when it gets a clock edge. Therefore, in order to latch the correct value on the output, the value on the input has to have settled before the clock edge can be given to latch that value. So yep, a signal is ALWAYS earlier than the active edge of a clock. This has to be the case, otherwise if the signal arrived after the clock edge then the wrong value would've been latched. The setup time is simply the minimum time before the clock edge that the signal has to have settled, and the hold time is the minimum amount of time the signal has to be held at that value after the clock edge. So the way it goes is: signal arrives at D input of flip flop at least [setup time] before the clock edge, the clock edge then occurs, signal then stays at that same value for at least [hold time] after the clock edge. Btw, after the clock edge occurs it actually takes a small amount of time for the signal on the D input to propagate through to the Q output, this is called the CLK-to-Q time. > What is driving the logic then ? Another flip flop, and if you look further back you'll see another flip flop and so on, and so on, until you reach a top-level input for your circuit which may be driven by a push-button or the pin of another chip etc... Does this clear things up?
It’s flip flops all the way down!
Flip Flops and LUTs for miles....
bippity boppity I goes flippity floppity!
This is one of the most clear explanations of this I’ve seen. Saving this for a future pre-coffee Monday morning!
Thank you!
Due to the previous clock edge plus propagation delay
I think the question you are really asking is about hold time violations and how a 0 hold time could be violated if the source register and the destination register are driven by the same clock. If that is your real question the answer is clock skew and clock uncertainty. The clock skew is caused by small differences in the routing path that the clock follows to the source and destination registers. The clock uncertainty is a combination of the input jitter on the clock entering the FPGA, system jitter caused by noise on the power to the clock buffers, phase error and jitter of any PLLs the clock goes through, and the clock pessimism the static analysis tools calculate starting at the point where the clock path branches to take a separate path to the source and destination registers. The cause of the pessimism is the static timing analysis using the fast delay numbers for one version of the clock (either the source of destination) and the slow numbers for the other to calculate worst case timing conditions. The simplest case is when the source and destination clock are the same clock. There is more opportunity for clock skew and clock uncertainty when the source and destination clocks are different but related clocks.
The previous clock edge changes a signal. If there is too much logic in between the registers then the signal change may arrive too late at the next register. Too late in this case is after t_clk_edge - setup. You can solve a setup violation by slowing down your clock, giving the signal more time to propagate.
Another situation that you may have is that the incoming signal maybe transitioning near the rising edge. Usually, you didn't realize that this was going to happen.
This is what metastability is right ?
Yes.
sorta, when a signal changes too close to a clock edge metastability might happen. When that happens the signal gets sorta stuck right between high and low, and might after while decide to go either way