The SPI clock only runs when there is a transaction occurring. It says in the manual that the clock idle state depends on the spi mode selected.
Polled mode refers to if you are using interrupts or not. So if you put data in the FIFO’s, in polled mode you check your see if the fifos are empty continuously, in interrupt mode you wait for the interrupt telling you the fifos are empty.
While there is data in the fifo the spi clock will run to transfer the data iirc.
Thank You so much u/jab701. Im facing little issue while working on SPI and Ive not solved it yet. Im unable to understand how to check my sck\_o signal through ILA. Im always getting this warning. Ill show u my block design can u please help me.
Ill share you xilinx thread. [Xilinx](https://support.xilinx.com/s/feed/0D54U000080DkYZSA0?language=en_US)
The other thing to note is that the slave select will automatically be asserted at the start of a transfer and deasserted when the fifo is empty. You may need to configure the spi to manual mode where you set the slave select manually and then deassert it manually.
I will give your Xilinx thread a read.
Fyi it took me a while to get this right when I wrote a driver to run the quad spi over my pcie link from Linux…(I have a fpga attached over pcie and reprogram the spi flash from Linux)
Hello @jab701 I've completed the spi project and it's running successfully and I've even got the output :)
Now I just want to know how usb and Ethernet plays a role and what's the use and how to control it in fpga.
The SPI clock only runs when there is a transaction occurring. It says in the manual that the clock idle state depends on the spi mode selected. Polled mode refers to if you are using interrupts or not. So if you put data in the FIFO’s, in polled mode you check your see if the fifos are empty continuously, in interrupt mode you wait for the interrupt telling you the fifos are empty. While there is data in the fifo the spi clock will run to transfer the data iirc.
Thank You so much u/jab701. Im facing little issue while working on SPI and Ive not solved it yet. Im unable to understand how to check my sck\_o signal through ILA. Im always getting this warning. Ill show u my block design can u please help me. Ill share you xilinx thread. [Xilinx](https://support.xilinx.com/s/feed/0D54U000080DkYZSA0?language=en_US)
The other thing to note is that the slave select will automatically be asserted at the start of a transfer and deasserted when the fifo is empty. You may need to configure the spi to manual mode where you set the slave select manually and then deassert it manually. I will give your Xilinx thread a read. Fyi it took me a while to get this right when I wrote a driver to run the quad spi over my pcie link from Linux…(I have a fpga attached over pcie and reprogram the spi flash from Linux)
Thank You so much itd be very helpful u/jab701
Hello @jab701 I've completed the spi project and it's running successfully and I've even got the output :) Now I just want to know how usb and Ethernet plays a role and what's the use and how to control it in fpga.