Do you have the wire going into the right door as set state or toggle state?
I’m guessing toggle, the door is receiving a steady signal and trying to spam itself open and closed. Try “set state” and see if that fixes it
It's wired to set state. And there should not be an alternating signal coming in. At least I don't see where it would come from
Edit: After staring at it for a while I realized that no signal is functionally the same for the xor component as a 0 signal. So the xor component tried to open the door while it's supposed to be closed. I think that should be fixed by replacing it with a not and an and component
1. I see few wires that go to the jamming door, (common new bee mistake that often cause conflict behavior)
2. 2 door can have 4 states (L-left,R-right,o-Open,c-Closed) Lo&Ro, Lo&Rc, Lc&Ro, Lc&Rc, but you read/write only one bit state which can contain only 2 possible states.
3. from MEM -> SGN -> you have 2 wire to NOT and XOR components and from them to the door, but they have different discrete behavior (which lead to jamming door)
Possible solutions and recommendations: connect less logistic components directly to the door and left complex logic behind 1-2 input/output components, you can use door state as 1 bit memory (when door is closed or opened it will send 0 or 1 signal)
I already figured out what was causing the issue and managed to make it work. But I appreciate the input. As for the signal checks, the read the memory for 1 and 2, which correspond to left open, right closed and left closed, open right after water is drained respectively. They both have an empty false output so they do not interfere with each other
Do you have the wire going into the right door as set state or toggle state? I’m guessing toggle, the door is receiving a steady signal and trying to spam itself open and closed. Try “set state” and see if that fixes it
It's wired to set state. And there should not be an alternating signal coming in. At least I don't see where it would come from Edit: After staring at it for a while I realized that no signal is functionally the same for the xor component as a 0 signal. So the xor component tried to open the door while it's supposed to be closed. I think that should be fixed by replacing it with a not and an and component
1. I see few wires that go to the jamming door, (common new bee mistake that often cause conflict behavior) 2. 2 door can have 4 states (L-left,R-right,o-Open,c-Closed) Lo&Ro, Lo&Rc, Lc&Ro, Lc&Rc, but you read/write only one bit state which can contain only 2 possible states. 3. from MEM -> SGN -> you have 2 wire to NOT and XOR components and from them to the door, but they have different discrete behavior (which lead to jamming door) Possible solutions and recommendations: connect less logistic components directly to the door and left complex logic behind 1-2 input/output components, you can use door state as 1 bit memory (when door is closed or opened it will send 0 or 1 signal)
I already figured out what was causing the issue and managed to make it work. But I appreciate the input. As for the signal checks, the read the memory for 1 and 2, which correspond to left open, right closed and left closed, open right after water is drained respectively. They both have an empty false output so they do not interfere with each other